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F-101, Mauryansh Elanza
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Mon to Fri 8:00 AM - 9:00 PM
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Mon to Fri 8:00 AM - 9:00 PM
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| Hiring For | (VLSI) Design Verification (DV) |
| Job Description | (VLSI) Design Verification (DV) |
| Desired Profile | Skills : Functional specifications of the IPs, subsystems and SOC, Reviewing and Revising, System Verilog, UVM, Performing RTL simulations using Synopsys and Cadence simulators, Performing UPF Notice Period: Immediate Joiners |
| Education | BE, B.Tech, ME, M.tech |
| Location | Bangalore, Hyderabad, Kochin, Pune |
| career@krazymantra.com |